This invention relates to a sense amplifier circuit to be used by a MOS (metal oxide semiconductor) memory device.
In a MOS semiconductor memory device, a minute potential difference appears between each pair of bit lines in a read out mode of the memory device. The minute potential difference must be amplified to a satisfactory level. To amplify this potential difference, a differential amplifier is usually used. The use of a differential amplifier, however, involves some problems, typically, considerable time required for the amplification, and unsatisfactory reliability of the amplifier.
For a better understanding of the prior art problems, a mirror load type differential amplifier, which has widely been used as the sense amplifier will be given referring to FIG. 1. The differential amplifier comprises a pair of mirror load type amplifier sections 7.sub.1 and 7.sub.2. The amplifier section 7.sub.1 is made up of a differential amplifier circuit 3.sub.1 and a current mirror circuit 6.sub.1 serving as a load for the amplifier circuit 3.sub.1. The amplifier section 7.sub.2 is similarly made up of a differential amplifier circuit 3.sub.2 and a current mirror circuit 6.sub.2 serving as a load for the amplifier circuit 3.sub.2. The amplifier circuits 3.sub.1 and 3.sub.2 comprise respectively pairs of n-channel MOS transistors 1.sub.1, and 2.sub.1, and 1.sub.2 and 2.sub.2. The load circuits 6.sub.1 and 6.sub.2 comprise respectively pairs of p-channel transistors 4.sub.1 and 4.sub.2, and 5.sub.1 and 5.sub.2. An n-channel MOS transistor 8.sub.1 is provided with the current path connected at one end to a junction S between the sources of the transistors 1.sub.1 and 2.sub.1, and at the other end to the reference potential VSS. The gate of the transistor 8.sub.1 is coupled to a chip enable signal CE. The n-channel MOS transistor 8.sub.2 is similarly connected in the differential amplifier section 7.sub.1. These transistors 8.sub.1 and 8.sub.2 serve as switching elements. An input voltage VI1 to the mirror load type differential amplifier is input to the gates of the transistors 1.sub.1 and 2.sub.1. An input voltage VI2 is input to the gates of the transistors 1.sub.2 and 2.sub.2. Output voltages VO1 and VO2 are derived from the junctions between the transistors 1.sub.1 and 4.sub.1, and 1.sub.2 and 4.sub.2, respectively. VDD indicates a positive power source potential. VSS a reference potential, for example, a ground potential.
The operation of the mirror load type differential amplifier thus constructed is as graphically illustrated in FIG. 2. The time td1 taken from the starting point of a potential difference .DELTA.VI till the output potential difference .DELTA.VO starts is very short. That is, this amplifier amplifies the input potential difference .DELTA.VI at a very high speed. An amplification factor of this type amplifier, however, is small. The amplitude, however, of the output signal .DELTA.VO of the amplifier is unsatisfactory. To cope with the problem, a plurality of the mirror load type amplifiers are arranged in a cascade fashion. This approach successfully solves the amplification factor problem, but creates another problem of the amplification speed. Signal delays of the respective amplifier stages are accumulated, so that the amplifying speed of the whole amplifier is low.
A graph shown in FIG. 3 illustrates variations of the input and output voltages VI1, VI2, VO1 and VO2, and a potential at the junction S in each mirror load differential amplifier section 7.sub.1 and 7.sub.2, in comparison with a waveform of an address signal. As shown, a drain-source voltage VDS or VO1, of the transistor 1.sub.1 or a drain-source voltage VDS, or VO1 of the transistor 1.sub.2 reaches about 8 V of the power source voltage VDD. FIG. 4 illustrates the relationship between the drain-source voltage VDS and the gate-source voltage VGS of the transistor of the differential amplifier circuit in each amplifier section. As seen from this figure, the maximum drain-source voltage VDS near 8 V is located in the critical region RD of the transistor. In this region, a great number of hot carriers are generated. When the transistor is operated in this region, the threshold voltage of the transistor fluctuates and latch-up phenomenon occurs. This results in deterioration of the reliability of the amplifier.